Search - verilog standard

[Other resource] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
Platform: | Size: 2279 | Author: 彭帅 | Hits:

[Other resource] IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE

Description: IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Platform: | Size: 380828 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] backward

Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Platform: | Size: 3072 | Author: 宋昆仑 | Hits:

[VHDL-FPGA-Verilog] bin2gry

Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Platform: | Size: 4096 | Author: 宋昆仑 | Hits:

[Books] ram_smi

Description: 关于RTL8208的传输协议及标准的VERILOG实现。-Transfer Protocol on the RTL8208 and standard Verilog realize.
Platform: | Size: 2048 | Author: 李国 | Hits:

[Embeded-SCM Develop] opb_psram_controller.tar

Description: opb接口sdram控制器源码，标准参考设计，verilog语言-OPB SDRAM controller source interface, the standard reference design, verilog language
Platform: | Size: 6144 | Author: 范俊 | Hits:

Description: 用FPGA实现uart的verilog源码，包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
Platform: | Size: 2048 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] 5Divide

Description: 用Verilog HDL语言写的标准的5分频程序，可以立即使用-Verilog HDL language used to write the standard procedure of 5 min frequency, you can immediately use
Platform: | Size: 172032 | Author: wangfanlion | Hits:

[Other] UART_VHDL

Description: 由于微电子学和计算机科学的迅速发展，给EDA(电子设计自动化)行业带来了巨大的变化。特别是进入20世纪90年代后，电子系统已经从电路板级系统集成发展成为包括ASIC、FPGA/CPLD和嵌入系统的多种模式。可以说EDA产业已经成为电子信息类产品的支柱产业。EDA之所以能蓬勃发展的关键因素之一就是采用了硬件描述语言(HDL)描述电路系统。就FPGA和CPLD开发而言，比较流行的HDL主要有Verilog HDL、VHDL、ABEL-HDL和 AHDL 等，其中VHDL和Verilog HDL因适合标准化的发展方向而最终成为IEEE标准。-As the microelectronics and the rapid development of computer science, to the EDA (electronic design automation) industry, has brought great changes. Especially the beginning of the 20th century, 90 years, the electronic system has moved from the circuit board-level systems integration to develop into, including ASIC, FPGA/CPLD and embedded systems a variety of modes. Can be said that EDA industry, electronic information products has become a pillar industry. EDA has been able to flourish, one of the key factors is the use of a hardware description language (HDL) description of the electronic circuitry. On the FPGA and CPLD development, the more popular HDL mainly Verilog HDL, VHDL, ABEL-HDL, and AHDL etc., in which VHDL and Verilog HDL because of the direction for the development of standardization eventually become IEEE standard.
Platform: | Size: 290816 | Author: lilei | Hits:

[Other] traffic

Description: 实现路口交通灯系统的控制方法很多，可以用标准逻辑器件，可编程控制器PLC，单片机等方案来实现。但是这些控制方法的功能修改及调试都需要硬件电路的支持，在一定程度上增加了功能修改及系统调试的困难。因此，在设计中采用EDA技术，应用目前广泛应用的Verilog HDL硬件电路描述语言，实现交通灯系统控制器的设计，利用MAX+PLUS 集成开发环境进行综合、仿真，并下载到CPLD可编程逻辑器件中，完成系统的控制作用。-Intersection traffic signal systems to achieve the control of many ways you can use standard logic devices, programmable logic controller PLC, microcontroller and other programs to achieve. However, the functions of these control methods require modification and debugging support for hardware circuit, to a certain extent, an increase of functional modifications and system debugging difficulties. Thus, in the design using EDA technologies, applications, the widely used Verilog HDL hardware circuit description language to realize the design of traffic signal system controller, using MAX+ PLUS a comprehensive integrated development environment, simulation, and downloaded to the CPLD programmable logic devices to complete the system control role.
Platform: | Size: 1024 | Author: 沈田 | Hits:

[VHDL-FPGA-Verilog] kzhdverilogyf

Description: 国内关于verilog hdl书讲解比较浅，没深度，对于读者应该查看verilog hdl英文标准-Nations on the book to explain verilog hdl more shallow, lacking depth, for English readers should see the standard verilog hdl
Platform: | Size: 299008 | Author: 翁志能 | Hits:

[VHDL-FPGA-Verilog] SystemVerilogEventRegionsRaceAvoidanceGuidelines.r

Description: The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This paper details common Verilog verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in- depth explanation of SystemVerilog event regions is included to help understand how race- reduction goals have been met. Important design & testbench coding guidelines are also included.-The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This paper details common Verilog verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in- depth explanation of SystemVerilog event regions is included to help understand how race- reduction goals have been met. Important design & testbench coding guidelines are also included.
Platform: | Size: 356352 | Author: 陈斌 | Hits:

[VHDL-FPGA-Verilog] PalnitkarVerilogHDL

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: Amir | Hits:

[VHDL-FPGA-Verilog] IEEE_standard_verilog

Description: 其中，Verilog硬件描述语言（HDL）的定义，在这个标准。 Verilog的HDL是一个正式的符号中的电子系统创建的各个阶段使用。因为它既是机读和人类可读的，它支持开发，验证，综合，硬件设计和测试，对数据通信的硬件设计，以及维修，改装和硬件采购。这个标准的主要对象是工具的实现者支持的语言和语言的高级用户。-The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification,synthesis, and testing of hardware designs the communication of hardware design data and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
Platform: | Size: 4159488 | Author: zhong | Hits:

[Other] CRC16_D8_m

Description: 用verilog实现的crc校验，符合标准-Crc check with verilog implementation, the standard
Platform: | Size: 1024 | Author: 张华 | Hits:

[VHDL-FPGA-Verilog] verilog_std

Description: verilog语言标准-verilog language standard
Platform: | Size: 1430528 | Author: ligong | Hits:

[VHDL-FPGA-Verilog] sell

Description: Verilog 实现自动售货机，现在，自动售货机产业正在走向信息化并进一步实现合理化。例如实行联机方式，通过电话线路将自动售货机内的库存信息及时地传送各营业点的电脑中，从而确保了商品的发送、补充以及商品选定的顺利进行-CLK: standard clock signal, in this case, the frequency for 4Hz Now, the vending machine industry is on her way to the information and further achieve rationalization. For example implements online mode, through telephone lines will vending machine in inventory information timely transmission each outlet in the computer, thus ensuring the goods delivered and supplement of goods, and selected smoothly
Platform: | Size: 1024 | Author: 李小明 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list